Verification Platform Engineer, Platform Architecture
Apple, Cupertino, California +1
- Pay
- Not listed by the employer
- Work type
- Onsite
- Level
- Not stated
- Area
- Infra, platform & SRE
- Posted
- Sep 2, 2026
Check my fit
See how your résumé lines up with this role: where you match, what's missing, and lines worth rewording.
About the role
Apple’s Platform Architecture group develops the next generation of Apple hardware and the tools to make it possible. Our team builds high-performance verification systems that accelerate the development of Apple silicon. We aim to push the boundaries of pre-silicon validation with simulation solutions that apply and extend principles from hardware emulation.
DESCRIPTION
This role bridges Apple's next-generation platform technology with DV methodology and tooling. We are seeking an engineer with background in Design Verification who is interested in cutting-edge verification techniques and comfortable rapidly prototyping solutions. In this role, you will enable transformational improvements to simulation throughput for DV workflows through testbench design, infrastructure improvements, and platform R&D.
MINIMUM QUALIFICATIONS
Bachelor’s degree in Computer Engineering, Electrical Engineering, or a related field (or equivalent practical experience). Experience with SystemVerilog and EDA tooling. Experience with software development (e.g., using C++) and scripting (e.g., Perl or Python).
PREFERRED QUALIFICATIONS
Master’s degree in Computer Engineering, Electrical Engineering, or another hardware-related field. 3+ years of relevant experience. Deep hands-on experience in Design Verification methodologies (UVM, DPI-C, testbench architecture). Experience applying LEC, linting / static analysis tools, waveform debugging, and simulation / emulation flows. Strong understanding of SystemVerilog simulation semantics (events, time, glitches); intuitive grasp for hardware representation (clocks, resets, latches). Strong communication skills, with a proven history of cross-functional collaboration across silicon engineering, design verification, and EDA development teams and organizational boundaries. Experience with software optimization, high-performance computing (HPC), co-simulation architectures, or hardware acceleration / emulation. Development of agentic pipelines, graphs, skills, or similar work enabling AI productivity for other engineers.
Similar roles at other companies
Verification Engineer
Delos DataPalo Alto
$160K–$240K / yr
Posted 22 days ago
Staff Digital Verification Engineer
Efficient ComputerSan Francisco, Bay Area OR Pittsburgh, PA OR Austin, TX +3
$160K–$245K / yr
Posted Sep 1, 2026
Pay not posted
Posted Jan 6, 2025
Pay not posted
Posted Jan 21, 2025
Listed; checked 2 days ago. First seen by us 2 days ago. Being listed doesn't mean the team is actively interviewing.