Lead Digital Verification Engineer

About the role

Efficient Computer is rethinking computing from the ground up to solve one of AI's biggest challenges: energy. Our Fabric architecture delivers a 10–100x improvement in energy efficiency for general-purpose computation, including AI, while supporting familiar programming languages and software frameworks—unlocking new possibilities for autonomous machines, intelligent infrastructure, wearables, and space systems. With our first processor, Electron E1, now shipping in volume and more than $97 million in Series B financing recently announced, we're accelerating customer deployments and scaling our architecture to data center performance. Join us to build the hardware and software that bring intelligence wherever it's needed and help shape the next generation of computing.

We are looking for an experienced Design Verification Lead to drive the functional verification of complex SoC/IP designs from specification through tapeout in a newly formed hardware engineering organization. You will own the verification strategy, define methodology standards, build and guide a team of verification engineers, and serve as the final authority on verification quality and sign-off readiness. This role demands a strong blend of technical depth in modern verification methodologies (UVM, embedded C and compiler generated trace driven testing) and the leadership ability to execute across a multi-block chip program on schedule The DV Lead will help shape our internal processes for building robust and verified designs, including the company’s second product line, which will scale computing performance and capability, while improving energy efficiency.

This is a unique opportunity to have an influence on our products and processes as we move from the initial stages of product development to market release and scaled volume production. Join our team and help us shape the future of computing at the edge and beyond!

Key Responsibilities

- Define the end-to-end verification strategy across block, subsystem, and full-chip levels aligned with tapeout milestones

- Author and review verification plans mapping specifications to features, stimulus strategies(traditional stimulus generation, compiler driven), coverage goals, and sign-off criteria

- Architect scalable UVM-based testbench environments including agents, scoreboards, reference models, and coverage monitors

- Drive constrained-random stimulus development targeting protocol interactions, concurrency, error injection, and corner cases

- Define and close functional coverage models through systematic hole analysis, targeted tests, seed optimization, and regression tuning

- Deploy SystemVerilog Assertions for protocol compliance, interface checks, and design invariants across all simulation runs

- Lead full-chip verification including boot sequences, interrupt handling, DMA flows, power-on reset, and multi-block interactions

- Ensure CDC, RDC, and multi-power-domain verification in coordination with specialist tools and teams