Member of Technical Staff - Microarchitectural Validation

What you will do

As a Member of the Technical Staff on the Design Verification & Validation team at Architect, you'll own the verification strategy behind AI-generated designs taping out on leading foundries. You'll work at the intersection of rigorous hardware verification and AI-driven design automation.

Review AI-driven test plan, and validation strategy for internal and external SoC projects.
Provide domain-specific expertise to our AI/ML teams, including architectural and microarchitectural checks, validation modularity, checkers, coverage models, and interface protocols — helping encode DV best practices into our AI-driven flows.
Independently define, drive, and coordinate validation, verification, and integration flows across multiple IPs, including checkpoints and collateral handoffs.
Collaborate with architecture, design, and AI/ML leads to generate simulation- and emulation-ready collateral that scales across projects.

What you need

Degree: Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or a closely related field.
Tapeout Experience: 5+ years (10+ preferred) working on advanced-node tapeouts at top chip companies or fast-moving silicon startups. End-to-end silicon delivery is a strong plus.
Verification Expertise: Deep expertise in verification/validation, emulation, and architectural and system-level verification of industry-standard IPs. Proven track record defining microarchitectural checkers and monitors, modeling IP and SoC validation platforms, and developing modular, reusable validation collateral.
Coding: Strong skills in SystemVerilog, UVM, and C/C++ for test environments. Python strongly preferred.
Subsystem Depth: Hands-on verification experience in at least one of the following areas:
ARM/AMBA protocols (APB, AHB, AXI, and ideally ACE for coherent CPU interfaces)
CPU subsystems – boot, interrupts, debug, coherency
Memory controllers and PHY – LPDDR/DDR interfaces, controller-level verification
On-chip interconnect / NoC — routing, arbitration, QoS, bandwidth
NPU / ML accelerator cores – datapath, scratchpad memory, DMA engines
Security IPs and/or working with secure enclaves
Methodology: Hands-on experience with simulation and emulation flows and methodologies. Experience mapping IP and SoC designs to FPGA prototypes for fast functional verification.
Execution: Excellent problem-solving, collaboration, and communication skills with strong attention to detail. Ability to work independently and drive cross-functional alignment.
Leadership: Ability and desire to lead the DV function over time as the team scales.

Expected Exposure (beyond the baseline above)

Candidates should also bring hands-on exposure to most of the following

Microarchitecture: Working knowledge of the architecture and microarchitecture of complex digital subsystems, such as CPUs, XPUs, cache-coherency fabrics (NoCs/switches), memory hierarchies, and high-speed I/O (HSIO) protocols.
Advanced Pre-Silicon Verification: Experience contributing to coverage-driven verification using advanced UVM environments, formal verification, and emulation to validate microarchitectural boundary conditions and corner cases.
Post-Silicon Debug: Participation in post-silicon triage and debug, mapping observed silicon behavior back to RTL using logic analyzers, oscilloscopes, and internal debug hooks.
End-to-End Debug: A track record of isolating and resolving hard HW/FW/SW interaction bugs, performance bottlenecks, or protocol violations, in pre-silicon environments and/or post-silicon bring-up.

Member of Technical Staff - Microarchitectural Validation

What you will do

Member of Technical Staff - Microarchitectural Validation

What you will do

What you need

Expected Exposure (beyond the baseline above)

Candidates should also bring hands-on exposure to most of the following

Nice to have

Pay and benefits

About Architect Labs

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