Member of Technical Staff - Formal Verification
Architect Labs, Palo Alto
What you will do
As a Member of Technical Staff - Formal Verification Engineer at Architect Labs, you'll own formal verification of the AI-generated chip design artifacts, from early specifications through tape-out. You'll turn design intent into assertions, build formal environments, and work directly with designers to formally verify complex designs.
- Develop and execute formal verification plans using AI for hardware blocks and subsystems. Identify critical properties, define the scope of verification, and establish clear criteria for closure.
- Work with the AI researchers to build Spec to SVA flows including test plans, formal testbenches that capture functional requirements, interface protocols, and corner cases. Review assumptions against the specification and the environment the block will operate in.
- Drive proofs to completion using abstraction, decomposition, invariants, and appropriate solver strategies. Diagnose inconclusive results and make difficult designs tractable without hiding the behavior you need to verify.