CODEC Video Compression Engineer/Developer

About the role

Who we are

Neros is a defense technology company rebuilding America’s drone industrial base. We design and manufacture high-performance unmanned systems that are tested in combat, iterated at startup speed, and built at massive scale. Our team culture is fast, hands-on, and obsessed with closing the gap between design and deployment.

As drones transform the character of warfare, Neros is delivering the systems the West needs to compete on the modern battlefield and deter the adversaries of democracy. We’re hiring engineers, operators, and builders who want to move fast, take on extreme ownership, and get capability into the hands of warfighters in months, not years.

What you will be doing

We are seeking a highly skilled CODEC Video Compression Engineer/Developer to build low cost FPV digital video, similar to DJI 04.

They will design, optimize, and implement low-latency advanced video compression algorithms while maintaining high visual quality, for real time video streaming application. You will work closely with cross-functional teams to deliver high-quality, low-latency wireless video. This role blends deep knowledge of video processing, mathematics, and software/hardware optimization to enable video transmission with minimum latency and reduced bandwidth usage.

Responsibilities

- Design and implementation of dual CPU/GPU hybrid video compression encoder architecture that can seamlessly combine SW and HW encoding engines

- Design, develop, and optimize video compression algorithms in C/C++, Assembly, Rust or similar languages

- Implement and optimize encoder/decoder pipelines for real-time applications

- Analyze and improve codec performance for speed, quality, and efficiency across CPU, GPU

- Perform error handling

- Conduct performance benchmarking, debugging, and quality assurance testing: Develop and use objective and subjective metrics to evaluate codec performance

- Collaborate with hardware and software teams to integrate CODEC solutions into products, using high-level synthesis, or FPGA/ASIC design flows

- Stay updated on emerging video standards, compression techniques, and industry trends

You should have the following

- Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or related field

- Solid understanding of video compression theory, motion estimation, transform coding, MC DCT, VBSMC, entropy coding, and rate control

- Codec implementation experience in developing actual software and hardware that encodes and decodes video data according to a specific compression format

- System Verilog experience (HLS/C++)

- Solid understanding of video compression standards (H.264, H.265/HEVC, H.266, VP9, AV1) and rate control algorithms

- Experience with hardware implementations using dedicated chips (FPGAs, ASICs, DSPs), and hybrid implementations using software for control logic with hardware accelerators GPUs (NVENC, NVDEC). Experience with GPU acceleration (CUDA, Vulkan, OpenCL)