Layout Scale-Up Engineer

You'll build the layout infrastructure that makes that scaling possible — PDK, layout compilers, parasitic extraction, hierarchical verification, and mask generation. This is a semiconductor physical-design role applied to superconducting hardware, not a quantum physics one.

• Build and own the PDK – layer stack, technology file, parametric cells (junctions, CPW, resonators, couplers, pads, airbridges/crossovers) — and their DRC/LVS decks
• Design a tile-based, hierarchical layout methodology: standardized reticle-compatible tiles, programmatic instantiation, and stitching for wafer-scale and multi-chip designs
• Write and maintain layout generators (Python/GDS or vendor EDA scripting) that turn architecture spec + frequency plan into DRC-clean GDSII/OASIS with zero manual drawing
• Own mask generation end-to-end: floorplan → hierarchical layout → DRC/LVS/PEX signoff → wafer map, test structures, PCM placement → mask data prep and tape-out package