Emulation Front-End Infrastructure Engineer

About the role

NVIDIA has been pioneering accelerated computing for more than two decades—from the invention of the GPU to breakthroughs in AI, high-performance computing, robotics, autonomous vehicles, and gaming. Our Emulation Infrastructure team builds scalable hardware development platforms and compilation flows that enable pre-silicon validation of NVIDIA’s most complex designs.

We are now looking for a Emulation Front-End Infrastructure Engineer to join our team onsite in Santa Clara, CA.

What you’ll be doing:

- Own and evolve front-end compilation, synthesis, and flow infrastructure for NVIDIA hardware emulation platforms.

- Develop, maintain, and automate robust compilation and synthesis flows using scripting and industry-leading EDA tools.

- Run, analyze, and debug regular compilation and synthesis regressions; help maintain RTL design stability in close partnership with logic designers.

- Explore and apply AI techniques to improve flow automation, triage compilation failures, identify recurring failure patterns, and accelerate root-cause analysis.

- Evaluate, deploy, and support EDA tools and methodologies for front-end implementation and emulation compilation.

- Diagnose complex compilation, elaboration, synthesis, and implementation issues, working closely with internal design teams and EDA vendors.

- Improve flow performance, reliability, scalability, usability, and observability across a large-scale hardware development environment.

What we need to see:

- A BS degree in Electrical Engineering, Computer Engineering, or a related field (or equivalent experience) with 5+ years of relevant experience; or an MS degree in a related field with 3+ years of relevant experience.

- Experience with RTL compilation, synthesis, front-end design implementation, and flow automation.

- Working proficiency in Verilog and SystemVerilog, including the ability to read, debug, and modify RTL for emulation needs.

- Strong understanding of RTL elaboration, synthesis, logic optimization, and front-end design methodologies.

- Hands-on experience with front-end synthesis and compilation EDA tools, including Synopsys Design Compiler, ZeBu Compiler, and Cadence HDL-ICE.

- Strong automation and scripting skills in Python, Perl, Tcl, shell scripting, and Makefile-based flows.

- Experience running high volumes of jobs on distributed compute farms using workload schedulers such as LSF or Slurm, and using revision-control systems such as Perforce or Git.

- Strong debugging, problem-solving, communication, and cross-functional collaboration skills.

Ways to stand out from the crowd:

- Experience with hardware-emulation compilation flows and runtime bring-up or debugging is a plus!

- Deep expertise with Synopsys Design Compiler, ZeBu Compiler, and Cadence HDL-ICE.

- Experience building scalable regression, reporting, monitoring, and flow-debug infrastructure.