DV - Staff Verification Engineer - Serdes
Eliyan, Bay Area, Vancouver or Toronto
About the job
Join the leading chiplet startup! As an Eliyan Staff Design Engineer, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow's chiplet-based systems with best-in-class power, area, manufacturability, and design flexibility. In this role you will lead the verification of Serdes. You will be developing state-of-the-art testbenches and unit/chip level test cases for best-in-class PHYs. You will own verification of TX/RX equalization and CDR. This is a hands-on technical leadership role. You'll define PHY verification architecture, write UVM/SV testbenches, and make sure that designs are bug free. You will work with a cross-functional team of experts. We offer a fun work environment with excellent benefits. ONSITE M-F.
Key Responsibilities
- Develop and execute verification plans for Serdes, other PHYs, DSP blocks, TX/RX equalization and CDR.
- Create and maintain SystemVerilog/UVM-based verification environments
- Write and debug SystemVerilog/UVM compliant test cases for block and chip level
- Maintain regression environments
- Collaborate with design team to ensure design quality