Platform Integration Engineer

About the role

Job Details:

Job Description:

About Central Engineering Group

The Central Engineering Group (CEG) is Intel's hub for driving innovation and excellence in silicon development. Focused on engineering solutions that power Intel's flagship products, CEG architects, designs, and validates IP foundational to Intel's broader technology portfolio. By joining this team, you will be part of a collaborative, inclusive environment driving advancements to strengthen Intel's leadership in the semiconductor industry.

Position Overview

As an IP Logic Design Engineer at Intel, you will play a pivotal role in developing high-quality IP blocks and subsystems for integration into full chip designs. You'll be responsible for creating cutting-edge logic designs, optimizing power, performance, and area, and ensuring seamless integration with the broader system. Your contributions will directly impact Intel's ability to deliver next-generation silicon solutions with speed, efficiency, and reliability.

Key Responsibilities

• Develop logic designs, register transfer level (RTL) coding, and simulation for IP blocks and subsystems for integration into full chip designs

• Define architecture and microarchitecture features and ensure their implementation in the design

• Optimize design logic to meet power, performance, area, and timing goals while maintaining physical implementation integrity

• Review verification plans and address RTL test failures to ensure accurate validation of design features

• Collaborate with physical design teams to address floorplan limitations and integrate designs seamlessly

• Drive quality assurance compliance to enable smooth IP-to-SoC handoff

What We're Looking For

To be successful in this role, you should demonstrate the following professional traits:

• Ability to collaborate effectively across cross-functional and geographically distributed teams • Strong attention to detail when reviewing verification plans and resolving design failures • A passion for innovation and continuous improvement in a fast-paced engineering environment

Qualifications:

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related STEM field with 6+ years of experience with RTL design and SystemVerilog OR Master's degree in relevant field with 4+ years of experience with RTL design and SystemVerilog

The experience must include:

• Industry-standard tools for front-end design, including synthesis, static timing analysis (STA), and lint checks

• AMBA protocols and coherent protocols such as IDI or CHI

• Hardware design concepts such as logic design, state machines, and network-on-chip architectures

Preferred Qualifications

• Experience with high-speed interconnect designs and power-performance optimization