Senior SoC Digital Verification Engineer, Multimedia Lab
TikTok, San Jose, California
What you will do
- Verification Planning: Deeply analyze architecture and design specifications to develop comprehensive and high-coverage module-level, subsystem-level, or SoC system-level Test Plans.
- Environment Development: Build from scratch or maintain highly reusable and automated advanced verification environments (Testbench) and components (Scoreboard, Monitor, Sequence, etc.) based on UVM methodology.
-Test Execution & Closure: Develop high-quality testcases, execute Constrained Random and Directed tests, and drive Functional and Code Coverage to 100% closure. -System-Level Verification: Responsible for Gate-Level Simulation (GLS) and SDF back-annotated timing simulation. Assist in FPGA prototyping and Hardware/Software co-debugging on Emulation platforms (e.g., Palladium/ZeBu).
- Flow Optimization: Develop and maintain regression testing scripts and automation tools to continuously improve the team's overall verification efficiency and compute resource utilization.