Senior Inference Optimization ML Engineer

About the role

At Rhoda AI, we’re building the next generation of generalist intelligent robots. We own the full robotics stack from high-performance hardware and robot systems to the infrastructure and state-of-the-art foundation world models that control our robots. Our robots are designed to be generalists capable of operating in complex, real-world environments and handling long-tail edge cases, made possible by our cutting edge research and end-to-end system design. We've raised over $450M and are investing aggressively in model research, infrastructure, hardware development, and manufacturing scale-up to make generalist robotics a reality.

Running large multimodal foundation models for a growing fleet of robots is expensive. We can't rely on one hardware vendor or the most expensive accelerators. We're looking for an Inference Optimization engineer to make Rhoda's models run fast, correctly, and cheaply on a wide range of hardware: AMD Instinct GPUs, Google TPUs, wafer-scale and dataflow accelerators, consumer GPUs like the RTX 5090, and the Jetson/Thor-class compute on our robots. You'll decide which chip runs which workload, and then make sure it runs well there. You'll work closely with the research, robotics, and infrastructure teams.

WHAT YOU'LL DO

- Own cost-efficient inference end-to-end. Make Rhoda's foundation models (vision, video, language, proprioception, action) faster and cheaper to run, measured in latency, throughput, and cost per inference.

- Port and optimize models for non-NVIDIA and lower-cost hardware. This includes AMD (ROCm, HIP, MIOpen/hipBLASLt, Composable Kernel), TPU (XLA, JAX, Pallas, PyTorch/XLA), wafer-scale and dataflow accelerators (their SDKs and compilers), and consumer Blackwell GPUs such as the RTX 5090 (FP8/FP4, small memory, multi-GPU setups over PCIe).

- Own on-robot inference. Deploy and optimize models on Jetson/Thor-class embedded compute under tight latency, power, thermal, and memory limits, and decide how work is split between the robot and the cloud to meet real-time control requirements.

- Evaluate hardware rigorously. Build cost/performance models (perf/$, perf/W, memory capacity and bandwidth, interconnect) for each chip and model family. Write clear recommendations on which hardware to buy or rent for serving, offline evaluation, and on-robot use.

- Build hardware-portable optimizations. Write and tune kernels that work across vendors where possible (Triton, Pallas, MLIR-based compilers) and vendor-specific ones where the speedup justifies it. Handle attention, KV cache, memory layout, and fused operators on every backend.

- Apply model compression for constrained hardware. Use quantization (INT8, FP8, FP4/MX formats, AWQ/GPTQ), pruning, distillation, and model or tensor parallelism so models fit and perform well on chips with less memory or limited data-type support.

- Keep results correct and consistent across backends. Build tests that check numerical parity, policy quality, and robot-relevant behaviour, so a model gives the same results whichever chip it runs on.