Memory Subsystem Engineer, MLA Technology

About the job

Annapurna Labs (our organization within AWS UC) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago—even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world.

In Annapurna Labs we are at the forefront of hardware/software co-design not just in Amazon Web Services (AWS) but across the industry. Our Machine Learning Accelerator (MLA) Technology is seeking a memory subsystem engineer who is interested in diving deep into the definition, design, validation, and data center operation of AWS’s next generation machine learning silicon and servers. Our team spans HBM, SRAM, and chiplet interconnects to enable the highest performing memory subsytems in the world.

As a senior member of our technology team, you will have opportunities to participate in the design and execution of HBM, SRAM, UCIe, and general high speed analog technologies, with the goal of creating the most stable machine learning platforms within AWS’s data centers. A senior memory subsytem engineer on our team needs to be able to work with vendors and internal design teams, understand complex memory and SERDES features, write/modify tests at scale, debug fleet wide issues, and collect data from manufacturing and the data center.