Memory Architect

About the role

NORMAL COMPUTING | BUILD WITH US

Normal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, Silicon Valley (Mountain View), and London.

THE ROLE

Hybrid: 3 days a week in the office, in Mountain View, New York or London.

Normal is building AI inference hardware based on our revolutionary new Thermo In-Memory Computing architecture and as Memory Architect you will lead the translation of these concepts from theory into silicon. You will have free rein to completely reimagine each element of a conventional memory; from the design and layout read/write paths, organization of memory arrays, to the development of a microarchitecture which seamlessly interleaves core memory operations with high performance compute. Ultimately, you will be responsible for delivering 100-1000× improvements in performance in AI inference.

You will report to the VP of Silicon Engineering and partner with scientists, microarchitects, physical design, and analog design engineers to implement a new standard cell library which combines existing digital compute primitives with Normal’s ThermoDRAM compute primitives. You will translate these new compute primitives into a highly performant Compute In-Memory System. You will own the technical relationship with major manufacturers from PDK acquisition through tapeout of test chips and production silicon.

This role requires a seasoned engineer with prior experience in memory technology but who understands that radical performance improvements require radical paradigm shifts.

WHAT YOU WILL OWN

- Architecture for Processing-In-Memory: Define the memory requirements and floorplan that enable in-memory compute capability. This includes not only read/write paths to ALUs but also novel memory primitives. Specify the read/write circuitry row/column decoders that enable novel memory and in-memory compute operations.

- Internal Bandwidth and Data Movement: Architect the local and global datapaths, segmented buses and on-die fabrics that move data between memory arrays and logic.

- Power Grid and Reliability: Own power distribution, power budgets, thermal limits, redundancy, and ECC so that peak memory and compute performance can be extracted from the system without damaging retention or yield

- PDK and Fab Path: Own access to process design kits and design rules and assess the limits and potential of architectural modifications which can be supported by existing design rules. Drive tapeout plan starting with an upcoming shuttle through test-chip content, schedule, and bring-up.

- Primitive Device Library: Partner with our analog engineers who build and characterize the primitive device library (write circuits, drivers, multiplexers). Set requirements and ensure design choices drive architectural performance considerations.