Senior Verification Engineer
AST SpaceMobile, Riga, Latvia +1
About the job
AST SpaceMobile and our global partners are building the first and only space-based cellular broadband network to be accessible by standard smartphones. Called SpaceMobile, this ultra-powerful network is being designed to provide connectivity at 4G/5G speeds everywhere on the planet – on land, at sea and in flight.
Position Overview
We are seeking a Senior FPGA Verification Engineer with 6-9 years of experience to design, develop, and execute comprehensive verification strategies for complex FPGA designs. This role requires strong hands-on expertise in SystemVerilog and UVM, testbench architecture, and cross-functional collaboration with design and system teams.
Key Responsibilities
- Develop and maintain SystemVerilog/UVM-based verification environments for FPGA block-level and top-level designs.
- Create and execute verification plans, directed and constrained-random test scenarios, assertions, and functional coverage.
- Perform simulation-based verification of FPGA designs using industry-standard simulators.
- Drive debug and root-cause analysis of functional issues and work closely with FPGA RTL designers.