Design Engineer - STA

About the role

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Job Description:

Be part of the Custom Silicon Design Team within Broadcom’s ASIC Products Division in beautiful Fort Collins, Colorado. Join a world-class engineering group developing custom CMOS ASICs for cutting-edge AI, Cellular, Networking, Computing, and Storage products. This position offers the opportunity to work on high-performance SoC designs operating at speeds exceeding 1 GHz, from concept through production.

Role Overview

This STA Engineering role focuses on chip-level timing architecture, analysis, and closure for advanced ASICs in deep sub-micron technologies. The position provides hands-on experience with the latest 3 nm and smaller process nodes and involves working across multiple design hierarchies to define, validate, and sign off complex timing environments for AI, computing, and networking SoCs.

Key Responsibilities

- Develop, validate, and maintain timing constraints for complex SoC designs across multiple modes and corners.

- Perform static timing analysis (STA) using industry-standard tools such as Synopsys PrimeTime or Cadence Tempus.

- Define and execute timing signoff methodologies, including process corners, derates, and uncertainties.

- Conduct pre- and post-route timing analysis, quality of results (QoR) evaluations, and closure verification.

- Generate and validate timing ECOs to achieve signoff-quality closure across PVT corners.

- Automate timing flows and analysis using Tcl and scripting languages such as Perl or Python.

- Collaborate with physical design, synthesis, and clock teams to ensure timing convergence and cross-domain consistency.

- Analyze and debug timing violations, signal integrity issues, and clock network challenges.

- Support power and performance optimization through informed timing analysis and constraint tuning.

- Ensure full compliance with timing signoff checklists, methodology, and documentation.

Technical Skills / Background

- Deep understanding of VLSI design principles and ASIC physical design fundamentals.

- Working knowledge of PLLs, clock network design, and timing elements such as flip-flops, latches, and memories.

- Proficiency in timing constraint creation, debugging, and validation.

- Strong understanding of RC networks, signal integrity, crosstalk delay, and noise analysis.

- Familiar with setup/hold analysis, multi-mode multi-corner (MMMC) timing, and ECO convergence.

- Exposure to advanced STA techniques, including POCV/SOCV/LVF, PBA, and SPICE correlation.

- Knowledge of timing libraries (CCS/ECSM/NLDM) and multi-input switching (MIS) effects.