Principal Physical Verification Engineer

About the role

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Job Description:

Principal Physical Design Engineer — ASIC Products Division (APD)

Location: San Jose, CA

Position Type: Full-Time

Who We Are — Physical Design Team in APD

Broadcom’s ASIC Products Division (APD) is the global leader in custom high-performance silicon solutions. We partner with the world’s most innovative technology companies—spanning hyper-scale cloud providers, AI pioneers, and tier-1 networking infrastructure leaders—to co-design and manufacture complex, custom ASICs that power the modern digital backbone.

The Physical Design team within APD is the world-class execution engine behind the industry's most advanced custom silicon. We push the limits of silicon technology by combining deep architectural expertise, advanced IP, cutting-edge physical design methodologies in 3nm/2nm nodes, and advanced 2.5D/3D chiplet integration to solve the most demanding compute and bandwidth challenges.We transform ultra-complex architectures into fully realized, high-yielding, first-pass silicon success.

Broadcom is searching for a Physical Verification PD Engineer to join the Asic Products Division. This position involves working with the advanced nodes to continue driving next generation Artificial Intelligence and Machine Learning ecosystems through our PCIe Switch Products, while leading world class performance, through our Enterprise Products. More specifically, this position will require in-depth knowledge of Foundry rules, DFM and experience in silicon tape-out and RTO tapeout.

Responsibilities:

- Execution of Chip level Physical Verification & Issue resolution

- Work on setting up DRM runsets for advance nodes and tool flows

- Manage and guide rules related to Top level Floorplan, I/O and bump planning

- Resolve physical design issues related to chip integration and assembly

- Provide technical direction on verification methodologies including DRC, LVS, ERC, and PERC

- Develop best practice guidelines for physical verification flows and runtime optimizations

Preferred qualifications:

- Hands-on experience in running physical verification (LVS,DRC,ERC,PERC)

- Experience with EDA tools and flows such as ICV, Calibre and Pegasus EDA tools

- Rule deck coding experience in ICV, Calibre or Pegasus EDA tools

- Experience in resolving chip level DRC/LVS/EMIR issues for advance nodes and tape out experience

- Electrical Rule Checking (ERC/PERC): Analyze ESD (Electrostatic Discharge), latch-up, floating gates, and power-domain isolation vulnerabilities.

- Density & Fill: Manage automated dummy metal, poly, and diffusion filling strategies to meet local and global density rules.