Design Engineer - Timing Methodology

About the role

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Job Description:

Broadcom's Timing Sign-Off group in Central Engineering is looking for an energetic and self-driven professional to join our team. Our group’s mission is to provide advanced timing sign-off methodologies to Broadcom’s chip teams with the goal of achieving best in class solutions with high yield and fully optimized margins. The candidate will participate and take ownership in Advanced Timing Sign-off methodology development and modeling for SOC and 3D/2.5D IC design. This includes complex studies and analysis of new concepts leading to design, development and improvement of existing and new solutions. The candidate should have experience in methodology development with deep knowledge of advanced silicon technologies, production testability and yield. The candidate should have Tapeout experience in high volume / high yield complex SOCs at advanced technology nodes. The candidate will be working closely with other experts across the company in a fast paced project oriented agile environment.

The candidate must have the ability to prioritize well, communicate clearly, proactively deliver practical and quality solutions on-time, work well with external and internal partners, and possess advanced IC design engineering skills. The candidate will be expected to work across multiple facets of projects and juggle multiple responsibilities at the same time.

Responsibilities:

- Develop and deploy timing signoff methodologies for advanced technology nodes.

- Design and implement SOC, 3D/2.5D IC & multi-die signoff solutions.

- Participate & Lead in EDA flow development for Primetime, Tempus & Innovus.

Qualifications:

The minimum engineering experience required is typically a BS degree in EE/CS with 12+ years of industry experience, or an MS degree or Ph.D. degree in EE/CS with 10+ years of industry experience.

Strong hands-on experience in Timing Signoff methodology development and ownership.

Strong hands-on experience in SOC and 3D/2.5D IC timing signoff.

Strong hands-on experience with statistical data analysis and modeling.

Strong hands-on experience in silicon technologies, testability and yield.

Strong hands-on experience with industry standard STA tools such as Primetime and Tempus.

Strong hands-on experience developing scripts in TCL, Python, Perl, Unix shell and flow automation.

Experience with revision control, issue management/defect tracking, continuous integration, and continuous delivery/deployment tools.

Strong analytical skills and extremely detail oriented, organized and methodical.

Strong communication skills. Clear and concise.