Principal Verification Engineer
Astera Labs, San Jose, California +1
The role
Astera Labs is seeking a Principal Design Verification Engineer with strong problem-solving abilities and a passion for developing robust verification methodologies for complex ASICs. The ideal candidate will have a solid background in SystemVerilog and experience with C/C++, Python, or similar scripting languages. This role involves full lifecycle verification—from planning and test development to debugging and coverage closure—contributing to the success of cutting-edge SoC designs.
What you will do
- Lead the functional verification of advanced ASICs, including test planning, development, execution, and coverage analysis.
- Collaborate closely with software and system validation teams to create and execute test plans on emulation platforms.
- Apply both directed and constrained-random verification techniques using SystemVerilog/UVM and other relevant tools.
- Debug test failures, analyze coverage results, and close functional coverage gaps to ensure comprehensive verification.